Copper electrodeposition in microelectronics

An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves supe...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Paneccasio, Jr, Vincent, Lin, Xuan, Figura, Paul, Hurtubise, Richard
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Paneccasio, Jr, Vincent
Lin, Xuan
Figura, Paul
Hurtubise, Richard
description An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07815786</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07815786</sourcerecordid><originalsourceid>FETCH-uspatents_grants_078157863</originalsourceid><addsrcrecordid>eNrjZNBxzi8oSC1SSM1JTS4pyk9JLcgvzizJzM9TyMxTyM1MLsqHyuRlJhfzMLCmJeYUp_JCaW4GBTfXEGcP3dLigsSS1LyS4vj0okQQZWBuYWhqbmFmTIQSAMNjK5Y</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Copper electrodeposition in microelectronics</title><source>USPTO Issued Patents</source><creator>Paneccasio, Jr, Vincent ; Lin, Xuan ; Figura, Paul ; Hurtubise, Richard</creator><creatorcontrib>Paneccasio, Jr, Vincent ; Lin, Xuan ; Figura, Paul ; Hurtubise, Richard ; Enthone Inc</creatorcontrib><description>An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7815786$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,309,781,803,886,64044</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7815786$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Paneccasio, Jr, Vincent</creatorcontrib><creatorcontrib>Lin, Xuan</creatorcontrib><creatorcontrib>Figura, Paul</creatorcontrib><creatorcontrib>Hurtubise, Richard</creatorcontrib><creatorcontrib>Enthone Inc</creatorcontrib><title>Copper electrodeposition in microelectronics</title><description>An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZNBxzi8oSC1SSM1JTS4pyk9JLcgvzizJzM9TyMxTyM1MLsqHyuRlJhfzMLCmJeYUp_JCaW4GBTfXEGcP3dLigsSS1LyS4vj0okQQZWBuYWhqbmFmTIQSAMNjK5Y</recordid><startdate>20101019</startdate><enddate>20101019</enddate><creator>Paneccasio, Jr, Vincent</creator><creator>Lin, Xuan</creator><creator>Figura, Paul</creator><creator>Hurtubise, Richard</creator><scope>EFH</scope></search><sort><creationdate>20101019</creationdate><title>Copper electrodeposition in microelectronics</title><author>Paneccasio, Jr, Vincent ; Lin, Xuan ; Figura, Paul ; Hurtubise, Richard</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078157863</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Paneccasio, Jr, Vincent</creatorcontrib><creatorcontrib>Lin, Xuan</creatorcontrib><creatorcontrib>Figura, Paul</creatorcontrib><creatorcontrib>Hurtubise, Richard</creatorcontrib><creatorcontrib>Enthone Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Paneccasio, Jr, Vincent</au><au>Lin, Xuan</au><au>Figura, Paul</au><au>Hurtubise, Richard</au><aucorp>Enthone Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Copper electrodeposition in microelectronics</title><date>2010-10-19</date><risdate>2010</risdate><abstract>An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07815786
source USPTO Issued Patents
title Copper electrodeposition in microelectronics
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T12%3A10%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Paneccasio,%20Jr,%20Vincent&rft.aucorp=Enthone%20Inc&rft.date=2010-10-19&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07815786%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true