Precise delay measurement through combinatorial logic

A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width...

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Bibliographische Detailangaben

Hauptverfasser:	Burke, Gary R, Chen, Yuan, Sheldon, Douglas J
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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