Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof
One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also in...
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| creator | Hu, Binghua Eugen, Mindricelu P Gilmore, Damien T Wofford, Bill A |
| description | One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer. |
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| fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07808071</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07808071</sourcerecordid><originalsourceid>FETCH-uspatents_grants_078080713</originalsourceid><addsrcrecordid>eNqNjDEOwjAMALswIOAP_gBSEUO7IxA77MhKnMYitavEKfB7QOIBTLfc3bJ5XWhkp-KrM83gaWZHEHFmGYDHKetMHvTJnsAiu7tQKYAGCCViSvoAyyQuAhdNaKwC5AcCFA8jWdRPHWBEqQGd1fzdUCYN62YRMBXa_Lhq4HS8Hs7bWiY0Eiu3IeMXbde3fdvt9n8ob_4LSA8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof</title><source>USPTO Issued Patents</source><creator>Hu, Binghua ; Eugen, Mindricelu P ; Gilmore, Damien T ; Wofford, Bill A</creator><creatorcontrib>Hu, Binghua ; Eugen, Mindricelu P ; Gilmore, Damien T ; Wofford, Bill A ; Texas Instruments Incorporated</creatorcontrib><description>One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7808071$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64038</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7808071$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hu, Binghua</creatorcontrib><creatorcontrib>Eugen, Mindricelu P</creatorcontrib><creatorcontrib>Gilmore, Damien T</creatorcontrib><creatorcontrib>Wofford, Bill A</creatorcontrib><creatorcontrib>Texas Instruments Incorporated</creatorcontrib><title>Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof</title><description>One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjDEOwjAMALswIOAP_gBSEUO7IxA77MhKnMYitavEKfB7QOIBTLfc3bJ5XWhkp-KrM83gaWZHEHFmGYDHKetMHvTJnsAiu7tQKYAGCCViSvoAyyQuAhdNaKwC5AcCFA8jWdRPHWBEqQGd1fzdUCYN62YRMBXa_Lhq4HS8Hs7bWiY0Eiu3IeMXbde3fdvt9n8ob_4LSA8</recordid><startdate>20101005</startdate><enddate>20101005</enddate><creator>Hu, Binghua</creator><creator>Eugen, Mindricelu P</creator><creator>Gilmore, Damien T</creator><creator>Wofford, Bill A</creator><scope>EFH</scope></search><sort><creationdate>20101005</creationdate><title>Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof</title><author>Hu, Binghua ; Eugen, Mindricelu P ; Gilmore, Damien T ; Wofford, Bill A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078080713</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Hu, Binghua</creatorcontrib><creatorcontrib>Eugen, Mindricelu P</creatorcontrib><creatorcontrib>Gilmore, Damien T</creatorcontrib><creatorcontrib>Wofford, Bill A</creatorcontrib><creatorcontrib>Texas Instruments Incorporated</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hu, Binghua</au><au>Eugen, Mindricelu P</au><au>Gilmore, Damien T</au><au>Wofford, Bill A</au><aucorp>Texas Instruments Incorporated</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof</title><date>2010-10-05</date><risdate>2010</risdate><abstract>One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T19%3A13%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Hu,%20Binghua&rft.aucorp=Texas%20Instruments%20Incorporated&rft.date=2010-10-05&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07808071%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |