Clock divider with a rational division factor
This disclosure can provide methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, i.e., 50% duty cycle, divided that are phase-aligned to the input clock. The non-integer divisors can include half-integer...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Haimzon, Avi |
description | This disclosure can provide methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, i.e., 50% duty cycle, divided that are phase-aligned to the input clock. The non-integer divisors can include half-integers, N/2, e.g. the division can be denoted 2:N. The value of N for each phase-aligned, balanced, divided clock can be distinct. The method can include generating an input clock signal having an input clock frequency, generating a secondary clock signal that transitions between a first state and a second state based on the input clock signal, generating a delayed secondary clock signal that is time delayed relative to the secondary clock signal, and generating the output clock signal that has a frequency that is a non-integer division of the input clock frequency. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07801263</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07801263</sourcerecordid><originalsourceid>FETCH-uspatents_grants_078012633</originalsourceid><addsrcrecordid>eNrjZNB1zslPzlZIySzLTEktUijPLMlQSFQoSizJzM9LzAGLFwOZCmmJySX5RTwMrGmJOcWpvFCam0HBzTXE2UO3tLggsSQ1r6Q4Pr0oEUQZmFsYGBqZGRsToQQAihgq5g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Clock divider with a rational division factor</title><source>USPTO Issued Patents</source><creator>Haimzon, Avi</creator><creatorcontrib>Haimzon, Avi ; Marvell Israel (M.I.S.L.) Ltd</creatorcontrib><description>This disclosure can provide methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, i.e., 50% duty cycle, divided that are phase-aligned to the input clock. The non-integer divisors can include half-integers, N/2, e.g. the division can be denoted 2:N. The value of N for each phase-aligned, balanced, divided clock can be distinct. The method can include generating an input clock signal having an input clock frequency, generating a secondary clock signal that transitions between a first state and a second state based on the input clock signal, generating a delayed secondary clock signal that is time delayed relative to the secondary clock signal, and generating the output clock signal that has a frequency that is a non-integer division of the input clock frequency.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7801263$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7801263$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Haimzon, Avi</creatorcontrib><creatorcontrib>Marvell Israel (M.I.S.L.) Ltd</creatorcontrib><title>Clock divider with a rational division factor</title><description>This disclosure can provide methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, i.e., 50% duty cycle, divided that are phase-aligned to the input clock. The non-integer divisors can include half-integers, N/2, e.g. the division can be denoted 2:N. The value of N for each phase-aligned, balanced, divided clock can be distinct. The method can include generating an input clock signal having an input clock frequency, generating a secondary clock signal that transitions between a first state and a second state based on the input clock signal, generating a delayed secondary clock signal that is time delayed relative to the secondary clock signal, and generating the output clock signal that has a frequency that is a non-integer division of the input clock frequency.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZNB1zslPzlZIySzLTEktUijPLMlQSFQoSizJzM9LzAGLFwOZCmmJySX5RTwMrGmJOcWpvFCam0HBzTXE2UO3tLggsSQ1r6Q4Pr0oEUQZmFsYGBqZGRsToQQAihgq5g</recordid><startdate>20100921</startdate><enddate>20100921</enddate><creator>Haimzon, Avi</creator><scope>EFH</scope></search><sort><creationdate>20100921</creationdate><title>Clock divider with a rational division factor</title><author>Haimzon, Avi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078012633</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Haimzon, Avi</creatorcontrib><creatorcontrib>Marvell Israel (M.I.S.L.) Ltd</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Haimzon, Avi</au><aucorp>Marvell Israel (M.I.S.L.) Ltd</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Clock divider with a rational division factor</title><date>2010-09-21</date><risdate>2010</risdate><abstract>This disclosure can provide methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, i.e., 50% duty cycle, divided that are phase-aligned to the input clock. The non-integer divisors can include half-integers, N/2, e.g. the division can be denoted 2:N. The value of N for each phase-aligned, balanced, divided clock can be distinct. The method can include generating an input clock signal having an input clock frequency, generating a secondary clock signal that transitions between a first state and a second state based on the input clock signal, generating a delayed secondary clock signal that is time delayed relative to the secondary clock signal, and generating the output clock signal that has a frequency that is a non-integer division of the input clock frequency.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_grants_07801263 |
source | USPTO Issued Patents |
title | Clock divider with a rational division factor |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T17%3A01%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Haimzon,%20Avi&rft.aucorp=Marvell%20Israel%20(M.I.S.L.)%20Ltd&rft.date=2010-09-21&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07801263%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |