Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection

Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection

An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive region...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: El-Kareh, Badih, Balster, Scott Gerard, Yasuda, Hiroshi, Schiekofer, Manfred
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator El-Kareh, Badih
Balster, Scott Gerard
Yasuda, Hiroshi
Schiekofer, Manfred
description An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07772057</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07772057</sourcerecordid><originalsourceid>FETCH-uspatents_grants_077720573</originalsourceid><addsrcrecordid>eNrjZKjyTS3JyE9RyE9TSEtMKspMTizJzEtXSMxTyMwrSU0vSixJTVFIzixKLs0sUSjPLMlQSAcKKRSn5qTpFhTll6Qml2Tm5-kANaSQqomHgTUtMac4lRdKczMouLmGOHvolhYXAJXnlRTHA40CUQbm5uZGBqbmxkQoAQDud0gM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection</title><source>USPTO Issued Patents</source><creator>El-Kareh, Badih ; Balster, Scott Gerard ; Yasuda, Hiroshi ; Schiekofer, Manfred</creator><creatorcontrib>El-Kareh, Badih ; Balster, Scott Gerard ; Yasuda, Hiroshi ; Schiekofer, Manfred ; Texas Instruments Incorporated</creatorcontrib><description>An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7772057$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7772057$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>El-Kareh, Badih</creatorcontrib><creatorcontrib>Balster, Scott Gerard</creatorcontrib><creatorcontrib>Yasuda, Hiroshi</creatorcontrib><creatorcontrib>Schiekofer, Manfred</creatorcontrib><creatorcontrib>Texas Instruments Incorporated</creatorcontrib><title>Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection</title><description>An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZKjyTS3JyE9RyE9TSEtMKspMTizJzEtXSMxTyMwrSU0vSixJTVFIzixKLs0sUSjPLMlQSAcKKRSn5qTpFhTll6Qml2Tm5-kANaSQqomHgTUtMac4lRdKczMouLmGOHvolhYXAJXnlRTHA40CUQbm5uZGBqbmxkQoAQDud0gM</recordid><startdate>20100810</startdate><enddate>20100810</enddate><creator>El-Kareh, Badih</creator><creator>Balster, Scott Gerard</creator><creator>Yasuda, Hiroshi</creator><creator>Schiekofer, Manfred</creator><scope>EFH</scope></search><sort><creationdate>20100810</creationdate><title>Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection</title><author>El-Kareh, Badih ; Balster, Scott Gerard ; Yasuda, Hiroshi ; Schiekofer, Manfred</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_077720573</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>El-Kareh, Badih</creatorcontrib><creatorcontrib>Balster, Scott Gerard</creatorcontrib><creatorcontrib>Yasuda, Hiroshi</creatorcontrib><creatorcontrib>Schiekofer, Manfred</creatorcontrib><creatorcontrib>Texas Instruments Incorporated</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>El-Kareh, Badih</au><au>Balster, Scott Gerard</au><au>Yasuda, Hiroshi</au><au>Schiekofer, Manfred</au><aucorp>Texas Instruments Incorporated</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection</title><date>2010-08-10</date><risdate>2010</risdate><abstract>An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07772057
source USPTO Issued Patents
title Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T18%3A43%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=El-Kareh,%20Badih&rft.aucorp=Texas%20Instruments%20Incorporated&rft.date=2010-08-10&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07772057%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true