Method and apparatus for serial link down detection

An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltag...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Bedwani, Serge R, Seh, Soon Seng, Tan, Siang Lin, Huffman, Amber, Gan, Chai Huat
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Bedwani, Serge R
Seh, Soon Seng
Tan, Siang Lin
Huffman, Amber
Gan, Chai Huat
description An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07724645</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07724645</sourcerecordid><originalsourceid>FETCH-uspatents_grants_077246453</originalsourceid><addsrcrecordid>eNrjZDD2TS3JyE9RSMwD4oKCxKLEktJihbT8IoXi1KLMxByFnMy8bIWU_PI8hZTUktTkksz8PB4G1rTEnOJUXijNzaDg5hri7KFbWlyQWJKaV1Icn16UCKIMzM2NTMxMTI2JUAIAwIstPw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for serial link down detection</title><source>USPTO Issued Patents</source><creator>Bedwani, Serge R ; Seh, Soon Seng ; Tan, Siang Lin ; Huffman, Amber ; Gan, Chai Huat</creator><creatorcontrib>Bedwani, Serge R ; Seh, Soon Seng ; Tan, Siang Lin ; Huffman, Amber ; Gan, Chai Huat ; Intel Corporation</creatorcontrib><description>An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7724645$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7724645$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Bedwani, Serge R</creatorcontrib><creatorcontrib>Seh, Soon Seng</creatorcontrib><creatorcontrib>Tan, Siang Lin</creatorcontrib><creatorcontrib>Huffman, Amber</creatorcontrib><creatorcontrib>Gan, Chai Huat</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><title>Method and apparatus for serial link down detection</title><description>An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDD2TS3JyE9RSMwD4oKCxKLEktJihbT8IoXi1KLMxByFnMy8bIWU_PI8hZTUktTkksz8PB4G1rTEnOJUXijNzaDg5hri7KFbWlyQWJKaV1Icn16UCKIMzM2NTMxMTI2JUAIAwIstPw</recordid><startdate>20100525</startdate><enddate>20100525</enddate><creator>Bedwani, Serge R</creator><creator>Seh, Soon Seng</creator><creator>Tan, Siang Lin</creator><creator>Huffman, Amber</creator><creator>Gan, Chai Huat</creator><scope>EFH</scope></search><sort><creationdate>20100525</creationdate><title>Method and apparatus for serial link down detection</title><author>Bedwani, Serge R ; Seh, Soon Seng ; Tan, Siang Lin ; Huffman, Amber ; Gan, Chai Huat</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_077246453</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Bedwani, Serge R</creatorcontrib><creatorcontrib>Seh, Soon Seng</creatorcontrib><creatorcontrib>Tan, Siang Lin</creatorcontrib><creatorcontrib>Huffman, Amber</creatorcontrib><creatorcontrib>Gan, Chai Huat</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bedwani, Serge R</au><au>Seh, Soon Seng</au><au>Tan, Siang Lin</au><au>Huffman, Amber</au><au>Gan, Chai Huat</au><aucorp>Intel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for serial link down detection</title><date>2010-05-25</date><risdate>2010</risdate><abstract>An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07724645
source USPTO Issued Patents
title Method and apparatus for serial link down detection
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T06%3A26%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Bedwani,%20Serge%20R&rft.aucorp=Intel%20Corporation&rft.date=2010-05-25&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07724645%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true