Integrated circuit package

Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsu...

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Hauptverfasser: Bayan, Jaime A, Poddar, Anindya
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creator Bayan, Jaime A
Poddar, Anindya
description Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07705476</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07705476</sourcerecordid><originalsourceid>FETCH-uspatents_grants_077054763</originalsourceid><addsrcrecordid>eNrjZJDyzCtJTS9KLElNUUjOLEouzSxRKEhMzk5MT-VhYE1LzClO5YXS3AwKbq4hzh66pcUFQPV5JcXxQI0gysDc3MDUxNzMmAglADY3I_0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit package</title><source>USPTO Issued Patents</source><creator>Bayan, Jaime A ; Poddar, Anindya</creator><creatorcontrib>Bayan, Jaime A ; Poddar, Anindya ; National Semiconductor Corporation</creatorcontrib><description>Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7705476$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,777,799,882,64018</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7705476$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Bayan, Jaime A</creatorcontrib><creatorcontrib>Poddar, Anindya</creatorcontrib><creatorcontrib>National Semiconductor Corporation</creatorcontrib><title>Integrated circuit package</title><description>Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZJDyzCtJTS9KLElNUUjOLEouzSxRKEhMzk5MT-VhYE1LzClO5YXS3AwKbq4hzh66pcUFQPV5JcXxQI0gysDc3MDUxNzMmAglADY3I_0</recordid><startdate>20100427</startdate><enddate>20100427</enddate><creator>Bayan, Jaime A</creator><creator>Poddar, Anindya</creator><scope>EFH</scope></search><sort><creationdate>20100427</creationdate><title>Integrated circuit package</title><author>Bayan, Jaime A ; Poddar, Anindya</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_077054763</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Bayan, Jaime A</creatorcontrib><creatorcontrib>Poddar, Anindya</creatorcontrib><creatorcontrib>National Semiconductor Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bayan, Jaime A</au><au>Poddar, Anindya</au><aucorp>National Semiconductor Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit package</title><date>2010-04-27</date><risdate>2010</risdate><abstract>Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.</abstract><oa>free_for_read</oa></addata></record>
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title Integrated circuit package
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T13%3A24%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Bayan,%20Jaime%20A&rft.aucorp=National%20Semiconductor%20Corporation&rft.date=2010-04-27&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07705476%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true