Data structure for enforcing consistent per-physical page cacheability attributes

Data structure for enforcing consistent per-physical page cacheability attributes

A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a...

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Hauptverfasser: Klaiber, Alexander C, Dunn, David
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Sprache:eng
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creator Klaiber, Alexander C
Dunn, David
description A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07676629</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07676629</sourcerecordid><originalsourceid>FETCH-uspatents_grants_076766293</originalsourceid><addsrcrecordid>eNqNjEEKwkAMAPfiQdQ_5AMFUdji2SpeBe-ShnQbKNslyR76ey34AC8zl2G24dmhI5hrJa_KMMwKnL8kyQlozibmnB0Ka1PGxYRwgoKJgZBGxl4m8QXQXaWvzrYPmwEn48PPuwD32-v6aKoVXFf2Toqrjm1sYzxdzn8kH_mkOYo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Data structure for enforcing consistent per-physical page cacheability attributes</title><source>USPTO Issued Patents</source><creator>Klaiber, Alexander C ; Dunn, David</creator><creatorcontrib>Klaiber, Alexander C ; Dunn, David</creatorcontrib><description>A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7676629$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7676629$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Klaiber, Alexander C</creatorcontrib><creatorcontrib>Dunn, David</creatorcontrib><title>Data structure for enforcing consistent per-physical page cacheability attributes</title><description>A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjEEKwkAMAPfiQdQ_5AMFUdji2SpeBe-ShnQbKNslyR76ey34AC8zl2G24dmhI5hrJa_KMMwKnL8kyQlozibmnB0Ka1PGxYRwgoKJgZBGxl4m8QXQXaWvzrYPmwEn48PPuwD32-v6aKoVXFf2Toqrjm1sYzxdzn8kH_mkOYo</recordid><startdate>20100309</startdate><enddate>20100309</enddate><creator>Klaiber, Alexander C</creator><creator>Dunn, David</creator><scope>EFH</scope></search><sort><creationdate>20100309</creationdate><title>Data structure for enforcing consistent per-physical page cacheability attributes</title><author>Klaiber, Alexander C ; Dunn, David</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_076766293</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Klaiber, Alexander C</creatorcontrib><creatorcontrib>Dunn, David</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Klaiber, Alexander C</au><au>Dunn, David</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data structure for enforcing consistent per-physical page cacheability attributes</title><date>2010-03-09</date><risdate>2010</risdate><abstract>A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.</abstract><oa>free_for_read</oa></addata></record>
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title Data structure for enforcing consistent per-physical page cacheability attributes
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T07%3A19%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Klaiber,%20Alexander%20C&rft.date=2010-03-09&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07676629%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true