Signal processing system with low bandwidth phase-locked loop

A signal processing system includes a phase-locked loop to provide an output signal used, for example, as a delta sigma modulator operating clock signal. In at least one embodiment, a frame clock that provides synchronization for one or more blocks of data is used by the phase-locked loop as a reference signal. Utilizing the frame clock as the reference signal allows the signal processing system to reduce the number of clock signals present in the signal processing system. In another embodiment, a phase-locked loop includes a loop filter that utilizes a sample and reset circuit, a feed forward integrator, and a feed forward stabilizer to provide a low frequency phase-locked loop bandwidth. In at least one embodiment, the feed forward integrator amplifies capacitance of the sample and reset circuit, which reduces the size of loop filter capacitors and, thus, allows on-chip capacitor integration.