Processing apparatus and integrated circuit to prevent illicit access and reverse engineering

Processing apparatus and integrated circuit to prevent illicit access and reverse engineering

A processing apparatus including an internal circuit having a CPU and internal devices and an external circuit including external devices provided externally of the internal circuit, and the like, and is aimed to prevent illicit access and reverse engineering. The internal circuit including a CPU, i...

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Hauptverfasser: Kawasaki, Yusuke, Sakurai, Hiroshi, Hashimoto, Shigeru, Yamamoto, Koken
Format: Patent
Sprache:eng
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creator Kawasaki, Yusuke
Sakurai, Hiroshi
Hashimoto, Shigeru
Yamamoto, Koken
description A processing apparatus including an internal circuit having a CPU and internal devices and an external circuit including external devices provided externally of the internal circuit, and the like, and is aimed to prevent illicit access and reverse engineering. The internal circuit including a CPU, internal devices and a bus line connecting the CPU to the internal devices and extending externally, and the external circuit including external devices provided externally of an externally extending portion of the bus line. The internal circuit further including a ciphering section provided at an entrance to an external side and ciphering addresses and data on the bus line by ciphering patterns according to a plurality of regions divided from an address space allotted to the entire external devices.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07657758</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07657758</sourcerecordid><originalsourceid>FETCH-uspatents_grants_076577583</originalsourceid><addsrcrecordid>eNqNTUsKAjEM7caFqHfIBQRBxroXxaULtyKhE0ugZEqSen474gFcPd5_GR43nRKZsWTAWlHRmwHKCCxOuVMaIbGmxg4-QVV6kzhwKZy6hGlufwuzo0ZAklmItE-uw-KFxWjzw1WAy_l-um6b1b4sbs9-McMuHoYYh-P-j8gHC7A95A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Processing apparatus and integrated circuit to prevent illicit access and reverse engineering</title><source>USPTO Issued Patents</source><creator>Kawasaki, Yusuke ; Sakurai, Hiroshi ; Hashimoto, Shigeru ; Yamamoto, Koken</creator><creatorcontrib>Kawasaki, Yusuke ; Sakurai, Hiroshi ; Hashimoto, Shigeru ; Yamamoto, Koken ; Fujitsu Limited</creatorcontrib><description>A processing apparatus including an internal circuit having a CPU and internal devices and an external circuit including external devices provided externally of the internal circuit, and the like, and is aimed to prevent illicit access and reverse engineering. The internal circuit including a CPU, internal devices and a bus line connecting the CPU to the internal devices and extending externally, and the external circuit including external devices provided externally of an externally extending portion of the bus line. The internal circuit further including a ciphering section provided at an entrance to an external side and ciphering addresses and data on the bus line by ciphering patterns according to a plurality of regions divided from an address space allotted to the entire external devices.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7657758$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7657758$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kawasaki, Yusuke</creatorcontrib><creatorcontrib>Sakurai, Hiroshi</creatorcontrib><creatorcontrib>Hashimoto, Shigeru</creatorcontrib><creatorcontrib>Yamamoto, Koken</creatorcontrib><creatorcontrib>Fujitsu Limited</creatorcontrib><title>Processing apparatus and integrated circuit to prevent illicit access and reverse engineering</title><description>A processing apparatus including an internal circuit having a CPU and internal devices and an external circuit including external devices provided externally of the internal circuit, and the like, and is aimed to prevent illicit access and reverse engineering. The internal circuit including a CPU, internal devices and a bus line connecting the CPU to the internal devices and extending externally, and the external circuit including external devices provided externally of an externally extending portion of the bus line. The internal circuit further including a ciphering section provided at an entrance to an external side and ciphering addresses and data on the bus line by ciphering patterns according to a plurality of regions divided from an address space allotted to the entire external devices.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNTUsKAjEM7caFqHfIBQRBxroXxaULtyKhE0ugZEqSen474gFcPd5_GR43nRKZsWTAWlHRmwHKCCxOuVMaIbGmxg4-QVV6kzhwKZy6hGlufwuzo0ZAklmItE-uw-KFxWjzw1WAy_l-um6b1b4sbs9-McMuHoYYh-P-j8gHC7A95A</recordid><startdate>20100202</startdate><enddate>20100202</enddate><creator>Kawasaki, Yusuke</creator><creator>Sakurai, Hiroshi</creator><creator>Hashimoto, Shigeru</creator><creator>Yamamoto, Koken</creator><scope>EFH</scope></search><sort><creationdate>20100202</creationdate><title>Processing apparatus and integrated circuit to prevent illicit access and reverse engineering</title><author>Kawasaki, Yusuke ; Sakurai, Hiroshi ; Hashimoto, Shigeru ; Yamamoto, Koken</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_076577583</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Kawasaki, Yusuke</creatorcontrib><creatorcontrib>Sakurai, Hiroshi</creatorcontrib><creatorcontrib>Hashimoto, Shigeru</creatorcontrib><creatorcontrib>Yamamoto, Koken</creatorcontrib><creatorcontrib>Fujitsu Limited</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kawasaki, Yusuke</au><au>Sakurai, Hiroshi</au><au>Hashimoto, Shigeru</au><au>Yamamoto, Koken</au><aucorp>Fujitsu Limited</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Processing apparatus and integrated circuit to prevent illicit access and reverse engineering</title><date>2010-02-02</date><risdate>2010</risdate><abstract>A processing apparatus including an internal circuit having a CPU and internal devices and an external circuit including external devices provided externally of the internal circuit, and the like, and is aimed to prevent illicit access and reverse engineering. The internal circuit including a CPU, internal devices and a bus line connecting the CPU to the internal devices and extending externally, and the external circuit including external devices provided externally of an externally extending portion of the bus line. The internal circuit further including a ciphering section provided at an entrance to an external side and ciphering addresses and data on the bus line by ciphering patterns according to a plurality of regions divided from an address space allotted to the entire external devices.</abstract><oa>free_for_read</oa></addata></record>
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title Processing apparatus and integrated circuit to prevent illicit access and reverse engineering
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T10%3A07%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kawasaki,%20Yusuke&rft.aucorp=Fujitsu%20Limited&rft.date=2010-02-02&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07657758%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true