Dual clock domain deskew circuit

Dual clock domain deskew circuit

In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower tha...

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Hauptverfasser: Klowden, Daniel S, Kumar, S. Reji, Panikkar, Adarsh, Vakil, Kersi H, Kolla, Abhimanyu
Format: Patent
Sprache:eng
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creator Klowden, Daniel S
Kumar, S. Reji
Panikkar, Adarsh
Vakil, Kersi H
Kolla, Abhimanyu
description In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07656983</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07656983</sourcerecordid><originalsourceid>FETCH-uspatents_grants_076569833</originalsourceid><addsrcrecordid>eNrjZFBwKU3MUUjOyU_OVkjJz03MzFNISS3OTi1XSM4sSi7NLOFhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwNzM1MzSwtiYCCUAHh0mDQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dual clock domain deskew circuit</title><source>USPTO Issued Patents</source><creator>Klowden, Daniel S ; Kumar, S. Reji ; Panikkar, Adarsh ; Vakil, Kersi H ; Kolla, Abhimanyu</creator><creatorcontrib>Klowden, Daniel S ; Kumar, S. Reji ; Panikkar, Adarsh ; Vakil, Kersi H ; Kolla, Abhimanyu ; Intel Corporation</creatorcontrib><description>In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7656983$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,309,781,803,886,64044</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7656983$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Klowden, Daniel S</creatorcontrib><creatorcontrib>Kumar, S. Reji</creatorcontrib><creatorcontrib>Panikkar, Adarsh</creatorcontrib><creatorcontrib>Vakil, Kersi H</creatorcontrib><creatorcontrib>Kolla, Abhimanyu</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><title>Dual clock domain deskew circuit</title><description>In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZFBwKU3MUUjOyU_OVkjJz03MzFNISS3OTi1XSM4sSi7NLOFhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwNzM1MzSwtiYCCUAHh0mDQ</recordid><startdate>20100202</startdate><enddate>20100202</enddate><creator>Klowden, Daniel S</creator><creator>Kumar, S. Reji</creator><creator>Panikkar, Adarsh</creator><creator>Vakil, Kersi H</creator><creator>Kolla, Abhimanyu</creator><scope>EFH</scope></search><sort><creationdate>20100202</creationdate><title>Dual clock domain deskew circuit</title><author>Klowden, Daniel S ; Kumar, S. Reji ; Panikkar, Adarsh ; Vakil, Kersi H ; Kolla, Abhimanyu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_076569833</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Klowden, Daniel S</creatorcontrib><creatorcontrib>Kumar, S. Reji</creatorcontrib><creatorcontrib>Panikkar, Adarsh</creatorcontrib><creatorcontrib>Vakil, Kersi H</creatorcontrib><creatorcontrib>Kolla, Abhimanyu</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Klowden, Daniel S</au><au>Kumar, S. Reji</au><au>Panikkar, Adarsh</au><au>Vakil, Kersi H</au><au>Kolla, Abhimanyu</au><aucorp>Intel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dual clock domain deskew circuit</title><date>2010-02-02</date><risdate>2010</risdate><abstract>In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.</abstract><oa>free_for_read</oa></addata></record>
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title Dual clock domain deskew circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-13T16%3A52%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Klowden,%20Daniel%20S&rft.aucorp=Intel%20Corporation&rft.date=2010-02-02&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07656983%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true