Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data

Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data

A serializer-deserializer and a method of deserializing data. In one embodiment, the serializer-deserializer includes: (1) an analog-to-digital converter configured to receive a serial data stream and provide a digital output based thereon, (2) a digital comparator coupled to the analog-to-digital c...

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1. Verfasser: Andreev, Alexander E
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creator Andreev, Alexander E
description A serializer-deserializer and a method of deserializing data. In one embodiment, the serializer-deserializer includes: (1) an analog-to-digital converter configured to receive a serial data stream and provide a digital output based thereon, (2) a digital comparator coupled to the analog-to-digital converter and configured to compare the digital output to an output table to yield candidate output bits, (3) a digital feedback equalizer coupled to the digital comparator and configured to generate the output table based on the candidate output bits and (4) a multiplexer coupled to the digital comparator and configured to select output bits from among the candidate output bits to form a discrete bit sequence.
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In one embodiment, the serializer-deserializer includes: (1) an analog-to-digital converter configured to receive a serial data stream and provide a digital output based thereon, (2) a digital comparator coupled to the analog-to-digital converter and configured to compare the digital output to an output table to yield candidate output bits, (3) a digital feedback equalizer coupled to the digital comparator and configured to generate the output table based on the candidate output bits and (4) a multiplexer coupled to the digital comparator and configured to select output bits from among the candidate output bits to form a discrete bit sequence.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7656325$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7656325$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Andreev, Alexander E</creatorcontrib><creatorcontrib>LSI Corporation</creatorcontrib><title>Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data</title><description>A serializer-deserializer and a method of deserializing data. In one embodiment, the serializer-deserializer includes: (1) an analog-to-digital converter configured to receive a serial data stream and provide a digital output based thereon, (2) a digital comparator coupled to the analog-to-digital converter and configured to compare the digital output to an output table to yield candidate output bits, (3) a digital feedback equalizer coupled to the digital comparator and configured to generate the output table based on the candidate output bits and (4) a multiplexer coupled to the digital comparator and configured to select output bits from among the candidate output bits to form a discrete bit sequence.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjLsKwkAQRbexEPUfptQiIIYkH-ADe-1lyE42A_sIsxNBv14Doq3V4XIPZ27ChYTR85OksJS_A9bv40B5Az3eOTpAGIRsChwxqn-AZceKHlDanpVaHYUAo4VA2icLqYNfbwpYVFyaWYc-0-rDhYHT8bo_F2MeUClqvjnBCdumrupyV5V_KC85SUNZ</recordid><startdate>20100202</startdate><enddate>20100202</enddate><creator>Andreev, Alexander E</creator><scope>EFH</scope></search><sort><creationdate>20100202</creationdate><title>Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data</title><author>Andreev, Alexander E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_076563253</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Andreev, Alexander E</creatorcontrib><creatorcontrib>LSI Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Andreev, Alexander E</au><aucorp>LSI Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data</title><date>2010-02-02</date><risdate>2010</risdate><abstract>A serializer-deserializer and a method of deserializing data. In one embodiment, the serializer-deserializer includes: (1) an analog-to-digital converter configured to receive a serial data stream and provide a digital output based thereon, (2) a digital comparator coupled to the analog-to-digital converter and configured to compare the digital output to an output table to yield candidate output bits, (3) a digital feedback equalizer coupled to the digital comparator and configured to generate the output table based on the candidate output bits and (4) a multiplexer coupled to the digital comparator and configured to select output bits from among the candidate output bits to form a discrete bit sequence.</abstract><oa>free_for_read</oa></addata></record>
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title Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data
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