Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions

Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided...

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Bibliographische Detailangaben

Hauptverfasser:	Boyd, Graeme B, Lye, William M, Cheng, Xun
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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