Method of making multi-chip electronic package with reduced line skew
A method of making an electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically...
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| creator | Memis, Irving |
| description | A method of making an electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. The method involves forming the line patterns in such a manner so as to reduce line skew. |
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| language | eng |
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| source | USPTO Issued Patents |
| title | Method of making multi-chip electronic package with reduced line skew |
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