System and method for sign-off timing closure of a VLSI chip

A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and assert...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kazda, Michael A, Kotecha, Pooja M, Matheny, Adam P, Reddy, Lakshmi, Trevillyan, Louise H, Villarrubia, Paul G
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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