Delay circuit

A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Asano, Shigetaka, Kikuta, Kazuyoshi
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
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