Integrated circuit testing methods using well bias modification

Methods for testing a semiconductor circuit including testing the circuit and modifying a well bias of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient...

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Bibliographische Detailangaben

Hauptverfasser:	Gattiker, Anne, Grosch, David A, Knox, Marc D, Motika, Franco, Nigh, Phil, Van Horn, Jody, Zuchowski, Paul S
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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