Interleaved memory cell with single-event-upset tolerance

A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second port...

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Bibliographische Detailangaben

Hauptverfasser:	de Jong, Jan L, Nguyen, Susan Xuan, Pang, Raymond C
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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