Variable clocking read capture for double data rate memory devices
A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and sec...
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| creator | Rao, Ashwin K Song, Sang-Won |
| description | A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway. |
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| fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07499368</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07499368</sourcerecordid><originalsourceid>FETCH-uspatents_grants_074993683</originalsourceid><addsrcrecordid>eNrjZHAKSyzKTEzKSVVIzslPzs7MS1coSk1MUUhOLCgpLUpVSMsvUkjJLwUpSEksSVQoSixJVchNzc0vqlRISS3LTE4t5mFgTUvMKU7lhdLcDApuriHOHrqlxQVA1XklxfHpRYkgysDcxNLS2MzCmAglAO0WMtc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Variable clocking read capture for double data rate memory devices</title><source>USPTO Issued Patents</source><creator>Rao, Ashwin K ; Song, Sang-Won</creator><creatorcontrib>Rao, Ashwin K ; Song, Sang-Won ; Texas Instruments Incorporated</creatorcontrib><description>A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.</description><language>eng</language><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7499368$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64015</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7499368$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Rao, Ashwin K</creatorcontrib><creatorcontrib>Song, Sang-Won</creatorcontrib><creatorcontrib>Texas Instruments Incorporated</creatorcontrib><title>Variable clocking read capture for double data rate memory devices</title><description>A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZHAKSyzKTEzKSVVIzslPzs7MS1coSk1MUUhOLCgpLUpVSMsvUkjJLwUpSEksSVQoSixJVchNzc0vqlRISS3LTE4t5mFgTUvMKU7lhdLcDApuriHOHrqlxQVA1XklxfHpRYkgysDcxNLS2MzCmAglAO0WMtc</recordid><startdate>20090303</startdate><enddate>20090303</enddate><creator>Rao, Ashwin K</creator><creator>Song, Sang-Won</creator><scope>EFH</scope></search><sort><creationdate>20090303</creationdate><title>Variable clocking read capture for double data rate memory devices</title><author>Rao, Ashwin K ; Song, Sang-Won</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_074993683</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Rao, Ashwin K</creatorcontrib><creatorcontrib>Song, Sang-Won</creatorcontrib><creatorcontrib>Texas Instruments Incorporated</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rao, Ashwin K</au><au>Song, Sang-Won</au><aucorp>Texas Instruments Incorporated</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Variable clocking read capture for double data rate memory devices</title><date>2009-03-03</date><risdate>2009</risdate><abstract>A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Variable clocking read capture for double data rate memory devices |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T16%3A32%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Rao,%20Ashwin%20K&rft.aucorp=Texas%20Instruments%20Incorporated&rft.date=2009-03-03&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07499368%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |