MCU with low power mode of operation

MCU with low power mode of operation

A low power system is disclosed for working in conjunction with a digital circuit that is disposed between positive and negative terminals. The system includes an internal voltage generator for increasing, for at least a first portion of the digital circuit, a voltage difference between the at least...

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1. Verfasser: Leung, Ka Y
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creator Leung, Ka Y
description A low power system is disclosed for working in conjunction with a digital circuit that is disposed between positive and negative terminals. The system includes an internal voltage generator for increasing, for at least a first portion of the digital circuit, a voltage difference between the at least a first portion of the digital circuit and the voltage on at least one of the positive and negative terminals during a low power mode of operation. This allows the voltage across the at least first portion of the digital circuit to be less than the full voltage across the positive and negative terminals.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07493505</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07493505</sourcerecordid><originalsourceid>FETCH-uspatents_grants_074935053</originalsourceid><addsrcrecordid>eNrjZFDxdQ5VKM8syVDIyS9XKMgvTy1SyM1PSVXIT1PIL0gtSizJzM_jYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcxNLY1MDUmAglAK0MJyY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MCU with low power mode of operation</title><source>USPTO Issued Patents</source><creator>Leung, Ka Y</creator><creatorcontrib>Leung, Ka Y ; Silicon Laboratories Inc</creatorcontrib><description>A low power system is disclosed for working in conjunction with a digital circuit that is disposed between positive and negative terminals. The system includes an internal voltage generator for increasing, for at least a first portion of the digital circuit, a voltage difference between the at least a first portion of the digital circuit and the voltage on at least one of the positive and negative terminals during a low power mode of operation. This allows the voltage across the at least first portion of the digital circuit to be less than the full voltage across the positive and negative terminals.</description><language>eng</language><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7493505$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7493505$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Leung, Ka Y</creatorcontrib><creatorcontrib>Silicon Laboratories Inc</creatorcontrib><title>MCU with low power mode of operation</title><description>A low power system is disclosed for working in conjunction with a digital circuit that is disposed between positive and negative terminals. The system includes an internal voltage generator for increasing, for at least a first portion of the digital circuit, a voltage difference between the at least a first portion of the digital circuit and the voltage on at least one of the positive and negative terminals during a low power mode of operation. This allows the voltage across the at least first portion of the digital circuit to be less than the full voltage across the positive and negative terminals.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZFDxdQ5VKM8syVDIyS9XKMgvTy1SyM1PSVXIT1PIL0gtSizJzM_jYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcxNLY1MDUmAglAK0MJyY</recordid><startdate>20090217</startdate><enddate>20090217</enddate><creator>Leung, Ka Y</creator><scope>EFH</scope></search><sort><creationdate>20090217</creationdate><title>MCU with low power mode of operation</title><author>Leung, Ka Y</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_074935053</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Leung, Ka Y</creatorcontrib><creatorcontrib>Silicon Laboratories Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Leung, Ka Y</au><aucorp>Silicon Laboratories Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MCU with low power mode of operation</title><date>2009-02-17</date><risdate>2009</risdate><abstract>A low power system is disclosed for working in conjunction with a digital circuit that is disposed between positive and negative terminals. The system includes an internal voltage generator for increasing, for at least a first portion of the digital circuit, a voltage difference between the at least a first portion of the digital circuit and the voltage on at least one of the positive and negative terminals during a low power mode of operation. This allows the voltage across the at least first portion of the digital circuit to be less than the full voltage across the positive and negative terminals.</abstract><oa>free_for_read</oa></addata></record>
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title MCU with low power mode of operation
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T08%3A04%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Leung,%20Ka%20Y&rft.aucorp=Silicon%20Laboratories%20Inc&rft.date=2009-02-17&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07493505%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true