System for simplifying layout processing

System for simplifying layout processing

A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit des...

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Hauptverfasser: Zhang, Youping, Lai, Weinong
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Sprache:eng
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creator Zhang, Youping
Lai, Weinong
description A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.
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title System for simplifying layout processing
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