Timing failure analysis in a semiconductor device having a pipelined architecture

A method of testing a semiconductor device having a pipelined architecture. Operation of a first pipeline stage of the semiconductor is disabled during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device. A second pipelined operation...

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Bibliographische Detailangaben

Hauptverfasser:	Iyengar, Vinay, Nataraj, Bindiganavale S
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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