Method and apparatus for testing data steering logic for data storage having independently addressable subunits

Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write...

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Hauptverfasser:	Mamileti, Lakshmikant, Krishnamurthy, Anand, Mumford, Clint Wayne, Patel, Sanjay B
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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