Method of optimizing customizable filler cells in an integrated circuit physical design process
A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Charlebois, Steven E Dunn, Paul E Rohrbaugh, III, George W |
description | A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07444609</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07444609</sourcerecordid><originalsourceid>FETCH-uspatents_grants_074446093</originalsourceid><addsrcrecordid>eNqNjDEKAjEQRdNYiHqHuYCw4KJYi2JjZ7_EZJIdGJOQmRR6eiN4AJv_fvH-X5rphjpnDzlALkpPelOK4Jpo7t0-GCEQM1ZwyCxACWzqqRirVfTgqLpGCmV-CTnL4FEoJig1OxRZm0WwLLj5cWXgcr6frtsmpe-TytSPvhgO4zjuh-PuD-UDe5E-cQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of optimizing customizable filler cells in an integrated circuit physical design process</title><source>USPTO Issued Patents</source><creator>Charlebois, Steven E ; Dunn, Paul E ; Rohrbaugh, III, George W</creator><creatorcontrib>Charlebois, Steven E ; Dunn, Paul E ; Rohrbaugh, III, George W ; International Business Machines Corporation</creatorcontrib><description>A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.</description><language>eng</language><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7444609$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7444609$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Charlebois, Steven E</creatorcontrib><creatorcontrib>Dunn, Paul E</creatorcontrib><creatorcontrib>Rohrbaugh, III, George W</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><title>Method of optimizing customizable filler cells in an integrated circuit physical design process</title><description>A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjDEKAjEQRdNYiHqHuYCw4KJYi2JjZ7_EZJIdGJOQmRR6eiN4AJv_fvH-X5rphjpnDzlALkpPelOK4Jpo7t0-GCEQM1ZwyCxACWzqqRirVfTgqLpGCmV-CTnL4FEoJig1OxRZm0WwLLj5cWXgcr6frtsmpe-TytSPvhgO4zjuh-PuD-UDe5E-cQ</recordid><startdate>20081028</startdate><enddate>20081028</enddate><creator>Charlebois, Steven E</creator><creator>Dunn, Paul E</creator><creator>Rohrbaugh, III, George W</creator><scope>EFH</scope></search><sort><creationdate>20081028</creationdate><title>Method of optimizing customizable filler cells in an integrated circuit physical design process</title><author>Charlebois, Steven E ; Dunn, Paul E ; Rohrbaugh, III, George W</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_074446093</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Charlebois, Steven E</creatorcontrib><creatorcontrib>Dunn, Paul E</creatorcontrib><creatorcontrib>Rohrbaugh, III, George W</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Charlebois, Steven E</au><au>Dunn, Paul E</au><au>Rohrbaugh, III, George W</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of optimizing customizable filler cells in an integrated circuit physical design process</title><date>2008-10-28</date><risdate>2008</risdate><abstract>A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_grants_07444609 |
source | USPTO Issued Patents |
title | Method of optimizing customizable filler cells in an integrated circuit physical design process |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T21%3A30%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Charlebois,%20Steven%20E&rft.aucorp=International%20Business%20Machines%20Corporation&rft.date=2008-10-28&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07444609%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |