Semiconductor integrated circuit having test circuitry with reduced power consumption

The present invention provides a semiconductor integrated circuits that can prevent causes arising a problem of the power consumption during the normal operation thereof. Solution: The present invention relates to a semiconductor integrated circuit having a plurality of memory device of the scan the...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Shidei, Tsunaaki
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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