Non-fenced list DMA command mechanism

A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one processor has a local storage. The DMAC i...

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Bibliographische Detailangaben

Hauptverfasser:	King, Matthew Edward, Liu, Peichum Peter, Mui, David, Yamazaki, Takeshi
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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