Method, system and apparatus for producing a clock with desired frequency characteristics

Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequen...

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1. Verfasser: Himeno, Toshihiko
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creator Himeno, Toshihiko
description Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequency which is on average some ratio of the frequency of the received clock signal, but still has a maximum frequency which is substantially equal to the frequency of the received clock signal. In one mode of operation, these circuits may output a clock signal substantially identical to a received clock signal, while in another mode of operation these circuits may output a clock signal substantially identical to a received clock during a time interval, thus reducing the average frequency of the output clock signal with respect to the received clock signal while maintaining the maximum frequency of the received clock signal.
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Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequency which is on average some ratio of the frequency of the received clock signal, but still has a maximum frequency which is substantially equal to the frequency of the received clock signal. In one mode of operation, these circuits may output a clock signal substantially identical to a received clock signal, while in another mode of operation these circuits may output a clock signal substantially identical to a received clock during a time interval, thus reducing the average frequency of the output clock signal with respect to the received clock signal while maintaining the maximum frequency of the received clock signal.</description><language>eng</language><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7421609$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7421609$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Himeno, Toshihiko</creatorcontrib><creatorcontrib>Kabushiki Kaisha Toshiba</creatorcontrib><title>Method, system and apparatus for producing a clock with desired frequency characteristics</title><description>Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequency which is on average some ratio of the frequency of the received clock signal, but still has a maximum frequency which is substantially equal to the frequency of the received clock signal. In one mode of operation, these circuits may output a clock signal substantially identical to a received clock signal, while in another mode of operation these circuits may output a clock signal substantially identical to a received clock during a time interval, thus reducing the average frequency of the output clock signal with respect to the received clock signal while maintaining the maximum frequency of the received clock signal.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNyz0OwjAMQOEuDAi4gw8AUvkRFTMCsbCxMCHLcZuIkgTbEertAYkDMH3Le-Pqembzyc1BBzV-AEYHmDMKWlFok0CW5AqF2AEC9Ynu8ArmwbEGYQet8LNwpAHIfy4ylqAWSKfVqMVeefZzUsHxcNmfFkUzGkfTWyf4pW42q-W23q3_SN6tETvn</recordid><startdate>20080902</startdate><enddate>20080902</enddate><creator>Himeno, Toshihiko</creator><scope>EFH</scope></search><sort><creationdate>20080902</creationdate><title>Method, system and apparatus for producing a clock with desired frequency characteristics</title><author>Himeno, Toshihiko</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_074216093</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Himeno, Toshihiko</creatorcontrib><creatorcontrib>Kabushiki Kaisha Toshiba</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Himeno, Toshihiko</au><aucorp>Kabushiki Kaisha Toshiba</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method, system and apparatus for producing a clock with desired frequency characteristics</title><date>2008-09-02</date><risdate>2008</risdate><abstract>Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequency which is on average some ratio of the frequency of the received clock signal, but still has a maximum frequency which is substantially equal to the frequency of the received clock signal. In one mode of operation, these circuits may output a clock signal substantially identical to a received clock signal, while in another mode of operation these circuits may output a clock signal substantially identical to a received clock during a time interval, thus reducing the average frequency of the output clock signal with respect to the received clock signal while maintaining the maximum frequency of the received clock signal.</abstract><oa>free_for_read</oa></addata></record>
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title Method, system and apparatus for producing a clock with desired frequency characteristics
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