Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages

An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated cir...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Patwardhan, Viraj A, Nguyen, Hau T, Kelkar, Nikhil
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Patwardhan, Viraj A
Nguyen, Hau T
Kelkar, Nikhil
description An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material. When the die is mounted to a substrate, the additional underfill material in the recess regions helps form more robust fillets than otherwise possible.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07413927</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07413927</sourcerecordid><originalsourceid>FETCH-uspatents_grants_074139273</originalsourceid><addsrcrecordid>eNqNikEKwjAQRbtxIeod5gIBtUJxKaJ4APcyJJM2OE2HTFLx9rbiAVx8Hv_xllU8iWDCXBT8kOb1IbaAIIkMinAgByU6Sj4wA7qONIwEjG_65qDUBztEV2ye3gv95JlGYrBdEKMWmUDQPrElXVcLj6y0-XFVwfVyP99MUcFMMeujTThj2xx29XHf1H8kH4NbQ7k</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages</title><source>USPTO Issued Patents</source><creator>Patwardhan, Viraj A ; Nguyen, Hau T ; Kelkar, Nikhil</creator><creatorcontrib>Patwardhan, Viraj A ; Nguyen, Hau T ; Kelkar, Nikhil ; National Semiconductor Corporation</creatorcontrib><description>An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material. When the die is mounted to a substrate, the additional underfill material in the recess regions helps form more robust fillets than otherwise possible.</description><language>eng</language><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7413927$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7413927$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Patwardhan, Viraj A</creatorcontrib><creatorcontrib>Nguyen, Hau T</creatorcontrib><creatorcontrib>Kelkar, Nikhil</creatorcontrib><creatorcontrib>National Semiconductor Corporation</creatorcontrib><title>Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages</title><description>An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material. When the die is mounted to a substrate, the additional underfill material in the recess regions helps form more robust fillets than otherwise possible.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNikEKwjAQRbtxIeod5gIBtUJxKaJ4APcyJJM2OE2HTFLx9rbiAVx8Hv_xllU8iWDCXBT8kOb1IbaAIIkMinAgByU6Sj4wA7qONIwEjG_65qDUBztEV2ye3gv95JlGYrBdEKMWmUDQPrElXVcLj6y0-XFVwfVyP99MUcFMMeujTThj2xx29XHf1H8kH4NbQ7k</recordid><startdate>20080819</startdate><enddate>20080819</enddate><creator>Patwardhan, Viraj A</creator><creator>Nguyen, Hau T</creator><creator>Kelkar, Nikhil</creator><scope>EFH</scope></search><sort><creationdate>20080819</creationdate><title>Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages</title><author>Patwardhan, Viraj A ; Nguyen, Hau T ; Kelkar, Nikhil</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_074139273</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Patwardhan, Viraj A</creatorcontrib><creatorcontrib>Nguyen, Hau T</creatorcontrib><creatorcontrib>Kelkar, Nikhil</creatorcontrib><creatorcontrib>National Semiconductor Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Patwardhan, Viraj A</au><au>Nguyen, Hau T</au><au>Kelkar, Nikhil</au><aucorp>National Semiconductor Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages</title><date>2008-08-19</date><risdate>2008</risdate><abstract>An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material. When the die is mounted to a substrate, the additional underfill material in the recess regions helps form more robust fillets than otherwise possible.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07413927
source USPTO Issued Patents
title Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T09%3A45%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Patwardhan,%20Viraj%20A&rft.aucorp=National%20Semiconductor%20Corporation&rft.date=2008-08-19&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07413927%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true