Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction

Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction

The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit.Systems and methods are disclosed for improving critical dime...

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Hauptverfasser: Amblard, Gilles, Dakshina-Murthy, Srikanteswara, Singh, Bhanwar
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Sprache:eng
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creator Amblard, Gilles
Dakshina-Murthy, Srikanteswara
Singh, Bhanwar
description The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit.Systems and methods are disclosed for improving critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER, and a trim etch component that facilitates achieving and/or restoring a target critical dimension.
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title Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction
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