Apparatus and methods for utilization of splittable execution units of a processor

A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit inst...

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Hauptverfasser: Sperber, Zeev, Savransky, Guillermo, Lahav, Sagi
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creator Sperber, Zeev
Savransky, Guillermo
Lahav, Sagi
description A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07389406</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07389406</sourcerecordid><originalsourceid>FETCH-uspatents_grants_073894063</originalsourceid><addsrcrecordid>eNqNiksKAjEMQLtxIeodcgFhYMTPchDFtbiXOJNqoTahSUA8vYx4AFcP3nvTcO5EsKK5ApYBnmQPHhQiV3BLOb3REhfgCCo5meEtE9CLev96L8l0rAhSuSdVrvMwiZiVFj_OAhwPl_1p6SpoVEyv94ojmk273a2adfvH8gEcOjmS</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Apparatus and methods for utilization of splittable execution units of a processor</title><source>USPTO Issued Patents</source><creator>Sperber, Zeev ; Savransky, Guillermo ; Lahav, Sagi</creator><creatorcontrib>Sperber, Zeev ; Savransky, Guillermo ; Lahav, Sagi ; Intel Corporation</creatorcontrib><description>A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.</description><language>eng</language><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7389406$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64015</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7389406$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Sperber, Zeev</creatorcontrib><creatorcontrib>Savransky, Guillermo</creatorcontrib><creatorcontrib>Lahav, Sagi</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><title>Apparatus and methods for utilization of splittable execution units of a processor</title><description>A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNiksKAjEMQLtxIeodcgFhYMTPchDFtbiXOJNqoTahSUA8vYx4AFcP3nvTcO5EsKK5ApYBnmQPHhQiV3BLOb3REhfgCCo5meEtE9CLev96L8l0rAhSuSdVrvMwiZiVFj_OAhwPl_1p6SpoVEyv94ojmk273a2adfvH8gEcOjmS</recordid><startdate>20080617</startdate><enddate>20080617</enddate><creator>Sperber, Zeev</creator><creator>Savransky, Guillermo</creator><creator>Lahav, Sagi</creator><scope>EFH</scope></search><sort><creationdate>20080617</creationdate><title>Apparatus and methods for utilization of splittable execution units of a processor</title><author>Sperber, Zeev ; Savransky, Guillermo ; Lahav, Sagi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_073894063</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Sperber, Zeev</creatorcontrib><creatorcontrib>Savransky, Guillermo</creatorcontrib><creatorcontrib>Lahav, Sagi</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sperber, Zeev</au><au>Savransky, Guillermo</au><au>Lahav, Sagi</au><aucorp>Intel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Apparatus and methods for utilization of splittable execution units of a processor</title><date>2008-06-17</date><risdate>2008</risdate><abstract>A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.</abstract><oa>free_for_read</oa></addata></record>
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title Apparatus and methods for utilization of splittable execution units of a processor
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T23%3A18%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Sperber,%20Zeev&rft.aucorp=Intel%20Corporation&rft.date=2008-06-17&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07389406%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true