Method for producing semiconductor memory devices and integrated memory device

The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: Willer, Josef
Format: Patent
Sprache:eng
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