Systems and methods for executing across at least one memory barrier employing speculative fills
Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Steely, Jr, Simon C Tierney, Gregory Edward |
description | Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07360069</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07360069</sourcerecordid><originalsourceid>FETCH-uspatents_grants_073600693</originalsourceid><addsrcrecordid>eNqNyz0KwkAQQOE0FqLeYS4gLAQi1mKw117HZDYu7B8zE3Fv7wY8gNVrvrduHtciSkEA4wiB9JVGAZsY6EPDrC5OgAMnqUDBE4pCilRlSFzgicyOKg7Zp7JgyXXzqO5NYJ33sm1WFr3Q7tdNA_35drrsZ8moFFXuE-MSc2g7Y7pj-wf5Arp_PtM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Systems and methods for executing across at least one memory barrier employing speculative fills</title><source>USPTO Issued Patents</source><creator>Steely, Jr, Simon C ; Tierney, Gregory Edward</creator><creatorcontrib>Steely, Jr, Simon C ; Tierney, Gregory Edward ; Hewlett-Packard Development Company, L.P</creatorcontrib><description>Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.</description><language>eng</language><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7360069$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7360069$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Steely, Jr, Simon C</creatorcontrib><creatorcontrib>Tierney, Gregory Edward</creatorcontrib><creatorcontrib>Hewlett-Packard Development Company, L.P</creatorcontrib><title>Systems and methods for executing across at least one memory barrier employing speculative fills</title><description>Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNyz0KwkAQQOE0FqLeYS4gLAQi1mKw117HZDYu7B8zE3Fv7wY8gNVrvrduHtciSkEA4wiB9JVGAZsY6EPDrC5OgAMnqUDBE4pCilRlSFzgicyOKg7Zp7JgyXXzqO5NYJ33sm1WFr3Q7tdNA_35drrsZ8moFFXuE-MSc2g7Y7pj-wf5Arp_PtM</recordid><startdate>20080415</startdate><enddate>20080415</enddate><creator>Steely, Jr, Simon C</creator><creator>Tierney, Gregory Edward</creator><scope>EFH</scope></search><sort><creationdate>20080415</creationdate><title>Systems and methods for executing across at least one memory barrier employing speculative fills</title><author>Steely, Jr, Simon C ; Tierney, Gregory Edward</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_073600693</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Steely, Jr, Simon C</creatorcontrib><creatorcontrib>Tierney, Gregory Edward</creatorcontrib><creatorcontrib>Hewlett-Packard Development Company, L.P</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Steely, Jr, Simon C</au><au>Tierney, Gregory Edward</au><aucorp>Hewlett-Packard Development Company, L.P</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Systems and methods for executing across at least one memory barrier employing speculative fills</title><date>2008-04-15</date><risdate>2008</risdate><abstract>Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_grants_07360069 |
source | USPTO Issued Patents |
title | Systems and methods for executing across at least one memory barrier employing speculative fills |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T13%3A24%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Steely,%20Jr,%20Simon%20C&rft.aucorp=Hewlett-Packard%20Development%20Company,%20L.P&rft.date=2008-04-15&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07360069%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |