Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module

Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module

A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge reg...

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Hauptverfasser: Grafe, Jurgen, Ludewig, Sylke, Thomas, Jochen, Weitz, Peter
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Sprache:eng
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creator Grafe, Jurgen
Ludewig, Sylke
Thomas, Jochen
Weitz, Peter
description A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07352057</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07352057</sourcerecordid><originalsourceid>FETCH-uspatents_grants_073520573</originalsourceid><addsrcrecordid>eNqNjDEOwjAQBN1QIOAP9wCQIqIoD0BB9NCjk-3EFvY58p15P46ggYpqip3ZtZKrjV4nMkVLyhCTKcGCw6enCZDAk9hMGIC_PO38DCyoH_tqGYhWXDIw1mnO9UMvOaM3P937f6tWIwa2uw83Cs7D7XQ5FJ5RLAnfp4wLmr7tjk3Xt38oL4w6RmI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module</title><source>USPTO Issued Patents</source><creator>Grafe, Jurgen ; Ludewig, Sylke ; Thomas, Jochen ; Weitz, Peter</creator><creatorcontrib>Grafe, Jurgen ; Ludewig, Sylke ; Thomas, Jochen ; Weitz, Peter ; Infineon Technologies AG</creatorcontrib><description>A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.</description><language>eng</language><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7352057$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7352057$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Grafe, Jurgen</creatorcontrib><creatorcontrib>Ludewig, Sylke</creatorcontrib><creatorcontrib>Thomas, Jochen</creatorcontrib><creatorcontrib>Weitz, Peter</creatorcontrib><creatorcontrib>Infineon Technologies AG</creatorcontrib><title>Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module</title><description>A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjDEOwjAQBN1QIOAP9wCQIqIoD0BB9NCjk-3EFvY58p15P46ggYpqip3ZtZKrjV4nMkVLyhCTKcGCw6enCZDAk9hMGIC_PO38DCyoH_tqGYhWXDIw1mnO9UMvOaM3P937f6tWIwa2uw83Cs7D7XQ5FJ5RLAnfp4wLmr7tjk3Xt38oL4w6RmI</recordid><startdate>20080401</startdate><enddate>20080401</enddate><creator>Grafe, Jurgen</creator><creator>Ludewig, Sylke</creator><creator>Thomas, Jochen</creator><creator>Weitz, Peter</creator><scope>EFH</scope></search><sort><creationdate>20080401</creationdate><title>Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module</title><author>Grafe, Jurgen ; Ludewig, Sylke ; Thomas, Jochen ; Weitz, Peter</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_073520573</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Grafe, Jurgen</creatorcontrib><creatorcontrib>Ludewig, Sylke</creatorcontrib><creatorcontrib>Thomas, Jochen</creatorcontrib><creatorcontrib>Weitz, Peter</creatorcontrib><creatorcontrib>Infineon Technologies AG</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Grafe, Jurgen</au><au>Ludewig, Sylke</au><au>Thomas, Jochen</au><au>Weitz, Peter</au><aucorp>Infineon Technologies AG</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module</title><date>2008-04-01</date><risdate>2008</risdate><abstract>A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.</abstract><oa>free_for_read</oa></addata></record>
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title Semiconductor module having an internal semiconductor chip stack, and method for producing said semiconductor module
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T14%3A17%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Grafe,%20Jurgen&rft.aucorp=Infineon%20Technologies%20AG&rft.date=2008-04-01&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07352057%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true