Indirect measurement of negative margin voltages in endurance testing of EEPROM cells

An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Ng, Philip S, Le, Minh V, Wang, Liqi, Son, Jinshu
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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