Method and architecture for synchronizing a path generator and/or extractor to a processor

Method and architecture for synchronizing a path generator and/or extractor to a processor

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhe...

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description An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07334147</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07334147</sourcerecordid><originalsourceid>FETCH-uspatents_grants_073341473</originalsourceid><addsrcrecordid>eNqNjD0KAkEMhaexEPUOuYCozMIeQBQbOysbCWN2ZkASSbKgnt5Z8AAWjw_e3zxcz-RF7oDcpKlUp-SjEgyiYG9ORYXrp3IGhCd6gUxMit7ittk00MsV02S4TCWVRGaiyzAb8GG0-nER4Hi47E_r0doRsdstK07Y9jF2u66Pf1S-_gE8NA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and architecture for synchronizing a path generator and/or extractor to a processor</title><source>USPTO Issued Patents</source><creator>Raza, S. Babar</creator><creatorcontrib>Raza, S. Babar ; Cypress Semiconductor Corporation</creatorcontrib><description>An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.</description><language>eng</language><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7334147$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7334147$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Raza, S. Babar</creatorcontrib><creatorcontrib>Cypress Semiconductor Corporation</creatorcontrib><title>Method and architecture for synchronizing a path generator and/or extractor to a processor</title><description>An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjD0KAkEMhaexEPUOuYCozMIeQBQbOysbCWN2ZkASSbKgnt5Z8AAWjw_e3zxcz-RF7oDcpKlUp-SjEgyiYG9ORYXrp3IGhCd6gUxMit7ittk00MsV02S4TCWVRGaiyzAb8GG0-nER4Hi47E_r0doRsdstK07Y9jF2u66Pf1S-_gE8NA</recordid><startdate>20080219</startdate><enddate>20080219</enddate><creator>Raza, S. Babar</creator><scope>EFH</scope></search><sort><creationdate>20080219</creationdate><title>Method and architecture for synchronizing a path generator and/or extractor to a processor</title><author>Raza, S. Babar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_073341473</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Raza, S. Babar</creatorcontrib><creatorcontrib>Cypress Semiconductor Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Raza, S. Babar</au><aucorp>Cypress Semiconductor Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and architecture for synchronizing a path generator and/or extractor to a processor</title><date>2008-02-19</date><risdate>2008</risdate><abstract>An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.</abstract><oa>free_for_read</oa></addata></record>
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title Method and architecture for synchronizing a path generator and/or extractor to a processor
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T11%3A44%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Raza,%20S.%20Babar&rft.aucorp=Cypress%20Semiconductor%20Corporation&rft.date=2008-02-19&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07334147%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true