Integrated thin film capacitor/inductor/interconnect system and method
A system and method for the fabrication of high reliability capacitors, inductors, and multi-layer interconnects (including resistors) on various thin film hybrid substrate surfaces is disclosed. The disclosed method first employs a thin metal layer deposited and patterned on the substrate. This thi...
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creator | Casper, Michael D Mraz, William B |
description | A system and method for the fabrication of high reliability capacitors, inductors, and multi-layer interconnects (including resistors) on various thin film hybrid substrate surfaces is disclosed. The disclosed method first employs a thin metal layer deposited and patterned on the substrate. This thin patterned layer is used to provide both lower electrodes for capacitor structures and interconnects between upper electrode components. Next, a dielectric layer is deposited over the thin patterned layer and the dielectric layer is patterned to open contact holes to the thin patterned layer. The upper electrode layers are then deposited and patterned on top of the dielectric. |
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The disclosed method first employs a thin metal layer deposited and patterned on the substrate. This thin patterned layer is used to provide both lower electrodes for capacitor structures and interconnects between upper electrode components. Next, a dielectric layer is deposited over the thin patterned layer and the dielectric layer is patterned to open contact holes to the thin patterned layer. The upper electrode layers are then deposited and patterned on top of the dielectric.</description><language>eng</language><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7327582$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7327582$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Casper, Michael D</creatorcontrib><creatorcontrib>Mraz, William B</creatorcontrib><creatorcontrib>UltraSource, Inc</creatorcontrib><title>Integrated thin film capacitor/inductor/interconnect system and method</title><description>A system and method for the fabrication of high reliability capacitors, inductors, and multi-layer interconnects (including resistors) on various thin film hybrid substrate surfaces is disclosed. The disclosed method first employs a thin metal layer deposited and patterned on the substrate. This thin patterned layer is used to provide both lower electrodes for capacitor structures and interconnects between upper electrode components. Next, a dielectric layer is deposited over the thin patterned layer and the dielectric layer is patterned to open contact holes to the thin patterned layer. The upper electrode layers are then deposited and patterned on top of the dielectric.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZHDzzCtJTS9KLElNUSjJyMxTSMvMyVVITixITM4syS_Sz8xLKU2GMEpSi5Lz8_JSk0sUiiuLS1JzFRLzUhRyU0sy8lN4GFjTEnOKU3mhNDeDgptriLOHbmlxAdDsvJLieKAlIMrA3NjI3NTCyJgIJQBAOzUi</recordid><startdate>20080205</startdate><enddate>20080205</enddate><creator>Casper, Michael D</creator><creator>Mraz, William B</creator><scope>EFH</scope></search><sort><creationdate>20080205</creationdate><title>Integrated thin film capacitor/inductor/interconnect system and method</title><author>Casper, Michael D ; Mraz, William B</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_073275823</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Casper, Michael D</creatorcontrib><creatorcontrib>Mraz, William B</creatorcontrib><creatorcontrib>UltraSource, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Casper, Michael D</au><au>Mraz, William B</au><aucorp>UltraSource, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated thin film capacitor/inductor/interconnect system and method</title><date>2008-02-05</date><risdate>2008</risdate><abstract>A system and method for the fabrication of high reliability capacitors, inductors, and multi-layer interconnects (including resistors) on various thin film hybrid substrate surfaces is disclosed. The disclosed method first employs a thin metal layer deposited and patterned on the substrate. This thin patterned layer is used to provide both lower electrodes for capacitor structures and interconnects between upper electrode components. Next, a dielectric layer is deposited over the thin patterned layer and the dielectric layer is patterned to open contact holes to the thin patterned layer. The upper electrode layers are then deposited and patterned on top of the dielectric.</abstract><oa>free_for_read</oa></addata></record> |
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title | Integrated thin film capacitor/inductor/interconnect system and method |
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