Timing violation debugging inside place and route tool
A method for developing a circuit design is disclosed. The method generally include the steps of (A) generating a violation display based on violation information provided from a place-and-route tool and (B) generating a layout display based on layout information provided from the place-and-route to...
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| Hauptverfasser: | , , |
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| Format: | Patent |
| Sprache: | eng |
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