Method and apparatus for handling errors in a processing system
A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a comp...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Kuramkote, Rajendra Marisetty, Suresh Yamada, Koichi Brenden, Scott Cheung, William |
description | A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07308610</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07308610</sourcerecordid><originalsourceid>FETCH-uspatents_grants_073086103</originalsourceid><addsrcrecordid>eNrjZLD3TS3JyE9RSMwD4oKCxKLEktJihbT8IoUMoFBOZl66QmpRUX5RsUJmnkKiQkFRfnJqcTFIuLiyuCQ1l4eBNS0xpziVF0pzMyi4uYY4e-iWFhcklqTmlRTHpxclgigDc2MDCzNDA2MilAAAVdUxzg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for handling errors in a processing system</title><source>USPTO Issued Patents</source><creator>Kuramkote, Rajendra ; Marisetty, Suresh ; Yamada, Koichi ; Brenden, Scott ; Cheung, William</creator><creatorcontrib>Kuramkote, Rajendra ; Marisetty, Suresh ; Yamada, Koichi ; Brenden, Scott ; Cheung, William ; Intel Corporation</creatorcontrib><description>A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7308610$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7308610$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kuramkote, Rajendra</creatorcontrib><creatorcontrib>Marisetty, Suresh</creatorcontrib><creatorcontrib>Yamada, Koichi</creatorcontrib><creatorcontrib>Brenden, Scott</creatorcontrib><creatorcontrib>Cheung, William</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><title>Method and apparatus for handling errors in a processing system</title><description>A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLD3TS3JyE9RSMwD4oKCxKLEktJihbT8IoUMoFBOZl66QmpRUX5RsUJmnkKiQkFRfnJqcTFIuLiyuCQ1l4eBNS0xpziVF0pzMyi4uYY4e-iWFhcklqTmlRTHpxclgigDc2MDCzNDA2MilAAAVdUxzg</recordid><startdate>20071211</startdate><enddate>20071211</enddate><creator>Kuramkote, Rajendra</creator><creator>Marisetty, Suresh</creator><creator>Yamada, Koichi</creator><creator>Brenden, Scott</creator><creator>Cheung, William</creator><scope>EFH</scope></search><sort><creationdate>20071211</creationdate><title>Method and apparatus for handling errors in a processing system</title><author>Kuramkote, Rajendra ; Marisetty, Suresh ; Yamada, Koichi ; Brenden, Scott ; Cheung, William</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_073086103</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Kuramkote, Rajendra</creatorcontrib><creatorcontrib>Marisetty, Suresh</creatorcontrib><creatorcontrib>Yamada, Koichi</creatorcontrib><creatorcontrib>Brenden, Scott</creatorcontrib><creatorcontrib>Cheung, William</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kuramkote, Rajendra</au><au>Marisetty, Suresh</au><au>Yamada, Koichi</au><au>Brenden, Scott</au><au>Cheung, William</au><aucorp>Intel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for handling errors in a processing system</title><date>2007-12-11</date><risdate>2007</risdate><abstract>A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_grants_07308610 |
source | USPTO Issued Patents |
title | Method and apparatus for handling errors in a processing system |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T23%3A10%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kuramkote,%20Rajendra&rft.aucorp=Intel%20Corporation&rft.date=2007-12-11&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07308610%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |