Redundant oscillator distribution in a multi-processor server system
The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a se...
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creator | Schmunkamp, Dietmar Wagner, Andreas Webel, Tobias Weiss, Ulrich |
description | The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) and the wiring from there to multiple, PLL-() free clock chips is provided. Instead of only one DCSC and one single wiring, two of them (---) are used combined with a further particular logic present on each clock chip, which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring. |
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In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) and the wiring from there to multiple, PLL-() free clock chips is provided. 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In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) and the wiring from there to multiple, PLL-() free clock chips is provided. Instead of only one DCSC and one single wiring, two of them (---) are used combined with a further particular logic present on each clock chip, which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.</abstract><oa>free_for_read</oa></addata></record> |
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title | Redundant oscillator distribution in a multi-processor server system |
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