Double byte select high voltage line for EEPROM memory block

A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select lin...

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Hauptverfasser:	Lambrache, Emil, Curry, Duncan, Pang, Richard F
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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