Double byte select high voltage line for EEPROM memory block
A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select lin...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Lambrache, Emil Curry, Duncan Pang, Richard F |
| description | A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between adjacent rows of memory cells. |
| format | Patent |
| fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07304890</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07304890</sourcerecordid><originalsourceid>FETCH-uspatents_grants_073048903</originalsourceid><addsrcrecordid>eNrjZLBxyS9NyklVSKosSVUoTs1JTS5RyMhMz1Aoy88pSUxPVcjJzEtVSMsvUnB1DQjy91XITc3NL6pUSMrJT87mYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDc2MDEwtLAmAglAEMWL6s</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Double byte select high voltage line for EEPROM memory block</title><source>USPTO Issued Patents</source><creator>Lambrache, Emil ; Curry, Duncan ; Pang, Richard F</creator><creatorcontrib>Lambrache, Emil ; Curry, Duncan ; Pang, Richard F ; Atmel Corporation</creatorcontrib><description>A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between adjacent rows of memory cells.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7304890$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7304890$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lambrache, Emil</creatorcontrib><creatorcontrib>Curry, Duncan</creatorcontrib><creatorcontrib>Pang, Richard F</creatorcontrib><creatorcontrib>Atmel Corporation</creatorcontrib><title>Double byte select high voltage line for EEPROM memory block</title><description>A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between adjacent rows of memory cells.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLBxyS9NyklVSKosSVUoTs1JTS5RyMhMz1Aoy88pSUxPVcjJzEtVSMsvUnB1DQjy91XITc3NL6pUSMrJT87mYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDc2MDEwtLAmAglAEMWL6s</recordid><startdate>20071204</startdate><enddate>20071204</enddate><creator>Lambrache, Emil</creator><creator>Curry, Duncan</creator><creator>Pang, Richard F</creator><scope>EFH</scope></search><sort><creationdate>20071204</creationdate><title>Double byte select high voltage line for EEPROM memory block</title><author>Lambrache, Emil ; Curry, Duncan ; Pang, Richard F</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_073048903</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Lambrache, Emil</creatorcontrib><creatorcontrib>Curry, Duncan</creatorcontrib><creatorcontrib>Pang, Richard F</creatorcontrib><creatorcontrib>Atmel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lambrache, Emil</au><au>Curry, Duncan</au><au>Pang, Richard F</au><aucorp>Atmel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Double byte select high voltage line for EEPROM memory block</title><date>2007-12-04</date><risdate>2007</risdate><abstract>A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between adjacent rows of memory cells.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_uspatents_grants_07304890 |
| source | USPTO Issued Patents |
| title | Double byte select high voltage line for EEPROM memory block |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-15T09%3A42%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lambrache,%20Emil&rft.aucorp=Atmel%20Corporation&rft.date=2007-12-04&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07304890%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |