Flash memory cell arrays having dual control gates per memory cell charge storage element

A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates...

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Bibliographische Detailangaben

1. Verfasser:	Harari, Eliyahou
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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