Pattern for improved visual inspection of semiconductor devices
A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a s...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Tuttle, Ralph C Plunket, Christopher Sean Slater, Jr, David B Negley, Gerald H Schneider, Thomas P |
description | A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07297561</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07297561</sourcerecordid><originalsourceid>FETCH-uspatents_grants_072975613</originalsourceid><addsrcrecordid>eNrjZLAPSCwpSS3KU0jLL1LIzC0oyi9LTVEoyywuTcxRyMwrLkhNLsnMz1PIT1MoTs3NTM7PSylNLgGqTUkty0xOLeZhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwNzI0tzUzNCYCCUAqvcykA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Pattern for improved visual inspection of semiconductor devices</title><source>USPTO Issued Patents</source><creator>Tuttle, Ralph C ; Plunket, Christopher Sean ; Slater, Jr, David B ; Negley, Gerald H ; Schneider, Thomas P</creator><creatorcontrib>Tuttle, Ralph C ; Plunket, Christopher Sean ; Slater, Jr, David B ; Negley, Gerald H ; Schneider, Thomas P ; Cree, Inc</creatorcontrib><description>A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7297561$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7297561$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tuttle, Ralph C</creatorcontrib><creatorcontrib>Plunket, Christopher Sean</creatorcontrib><creatorcontrib>Slater, Jr, David B</creatorcontrib><creatorcontrib>Negley, Gerald H</creatorcontrib><creatorcontrib>Schneider, Thomas P</creatorcontrib><creatorcontrib>Cree, Inc</creatorcontrib><title>Pattern for improved visual inspection of semiconductor devices</title><description>A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLAPSCwpSS3KU0jLL1LIzC0oyi9LTVEoyywuTcxRyMwrLkhNLsnMz1PIT1MoTs3NTM7PSylNLgGqTUkty0xOLeZhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwNzI0tzUzNCYCCUAqvcykA</recordid><startdate>20071120</startdate><enddate>20071120</enddate><creator>Tuttle, Ralph C</creator><creator>Plunket, Christopher Sean</creator><creator>Slater, Jr, David B</creator><creator>Negley, Gerald H</creator><creator>Schneider, Thomas P</creator><scope>EFH</scope></search><sort><creationdate>20071120</creationdate><title>Pattern for improved visual inspection of semiconductor devices</title><author>Tuttle, Ralph C ; Plunket, Christopher Sean ; Slater, Jr, David B ; Negley, Gerald H ; Schneider, Thomas P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_072975613</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Tuttle, Ralph C</creatorcontrib><creatorcontrib>Plunket, Christopher Sean</creatorcontrib><creatorcontrib>Slater, Jr, David B</creatorcontrib><creatorcontrib>Negley, Gerald H</creatorcontrib><creatorcontrib>Schneider, Thomas P</creatorcontrib><creatorcontrib>Cree, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tuttle, Ralph C</au><au>Plunket, Christopher Sean</au><au>Slater, Jr, David B</au><au>Negley, Gerald H</au><au>Schneider, Thomas P</au><aucorp>Cree, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Pattern for improved visual inspection of semiconductor devices</title><date>2007-11-20</date><risdate>2007</risdate><abstract>A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_grants_07297561 |
source | USPTO Issued Patents |
title | Pattern for improved visual inspection of semiconductor devices |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T23%3A41%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Tuttle,%20Ralph%20C&rft.aucorp=Cree,%20Inc&rft.date=2007-11-20&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07297561%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |