Method of modeling circuit cells for powergrid analysis

Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node voltages and capacitances to respective parts of the cell, are determined for each internal node of the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Qi, Xiaoning, Trivedi, Anuj, Yan, Kenneth Y
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Qi, Xiaoning
Trivedi, Anuj
Yan, Kenneth Y
description Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node voltages and capacitances to respective parts of the cell, are determined for each internal node of the cell. Current distribution coefficients may also be determined for each resistor in the cell. Using the distribution coefficients, internal cell capacitances are modeled as port capacitors. Resistive elements are modeled as a resistor network having no internal nodes. Transistor elements are modeled as port current sources. Such a model permits back calculation of internal node voltages and currents.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07283943</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07283943</sourcerecordid><originalsourceid>FETCH-uspatents_grants_072839433</originalsourceid><addsrcrecordid>eNrjZDD3TS3JyE9RyE9TyM1PSc3JzEtXSM4sSi7NLFFITs3JKVZIyy9SKMgvTy1KL8pMUUjMS8ypLM4s5mFgTUvMKU7lhdLcDApuriHOHrqlxQWJJal5JcXx6UWJIMrA3MjC2NLE2JgIJQCpwC79</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of modeling circuit cells for powergrid analysis</title><source>USPTO Issued Patents</source><creator>Qi, Xiaoning ; Trivedi, Anuj ; Yan, Kenneth Y</creator><creatorcontrib>Qi, Xiaoning ; Trivedi, Anuj ; Yan, Kenneth Y ; Sun Microsystems, Inc</creatorcontrib><description>Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node voltages and capacitances to respective parts of the cell, are determined for each internal node of the cell. Current distribution coefficients may also be determined for each resistor in the cell. Using the distribution coefficients, internal cell capacitances are modeled as port capacitors. Resistive elements are modeled as a resistor network having no internal nodes. Transistor elements are modeled as port current sources. Such a model permits back calculation of internal node voltages and currents.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7283943$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7283943$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Qi, Xiaoning</creatorcontrib><creatorcontrib>Trivedi, Anuj</creatorcontrib><creatorcontrib>Yan, Kenneth Y</creatorcontrib><creatorcontrib>Sun Microsystems, Inc</creatorcontrib><title>Method of modeling circuit cells for powergrid analysis</title><description>Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node voltages and capacitances to respective parts of the cell, are determined for each internal node of the cell. Current distribution coefficients may also be determined for each resistor in the cell. Using the distribution coefficients, internal cell capacitances are modeled as port capacitors. Resistive elements are modeled as a resistor network having no internal nodes. Transistor elements are modeled as port current sources. Such a model permits back calculation of internal node voltages and currents.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDD3TS3JyE9RyE9TyM1PSc3JzEtXSM4sSi7NLFFITs3JKVZIyy9SKMgvTy1KL8pMUUjMS8ypLM4s5mFgTUvMKU7lhdLcDApuriHOHrqlxQWJJal5JcXx6UWJIMrA3MjC2NLE2JgIJQCpwC79</recordid><startdate>20071016</startdate><enddate>20071016</enddate><creator>Qi, Xiaoning</creator><creator>Trivedi, Anuj</creator><creator>Yan, Kenneth Y</creator><scope>EFH</scope></search><sort><creationdate>20071016</creationdate><title>Method of modeling circuit cells for powergrid analysis</title><author>Qi, Xiaoning ; Trivedi, Anuj ; Yan, Kenneth Y</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_072839433</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Qi, Xiaoning</creatorcontrib><creatorcontrib>Trivedi, Anuj</creatorcontrib><creatorcontrib>Yan, Kenneth Y</creatorcontrib><creatorcontrib>Sun Microsystems, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Qi, Xiaoning</au><au>Trivedi, Anuj</au><au>Yan, Kenneth Y</au><aucorp>Sun Microsystems, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of modeling circuit cells for powergrid analysis</title><date>2007-10-16</date><risdate>2007</risdate><abstract>Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node voltages and capacitances to respective parts of the cell, are determined for each internal node of the cell. Current distribution coefficients may also be determined for each resistor in the cell. Using the distribution coefficients, internal cell capacitances are modeled as port capacitors. Resistive elements are modeled as a resistor network having no internal nodes. Transistor elements are modeled as port current sources. Such a model permits back calculation of internal node voltages and currents.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07283943
source USPTO Issued Patents
title Method of modeling circuit cells for powergrid analysis
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T13%3A49%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Qi,%20Xiaoning&rft.aucorp=Sun%20Microsystems,%20Inc&rft.date=2007-10-16&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07283943%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true