Content addressable memory including a dual mode cycle boundary latch

A content addressable memory (CAM) system is disclosed including a dual mode cycle boundary latch (CBL). The CBL includes a master latch coupled to a slave latch. The CBL operates in a high speed functional mode and a lower speed test mode. In the high speed functional mode, input data bypasses the...

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Bibliographische Detailangaben

Hauptverfasser:	Khan, Masood Ahmed, Lee, Michael Ju Hyeok, Seewann, Ed
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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