Clearance hole size adjustment for impedance control in multilayer electronic packaging and printed circuit boards

Clearance hole size adjustment for impedance control in multilayer electronic packaging and printed circuit boards

The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the cleara...

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Hauptverfasser: Dyckman, Warren D, LaFontant, Gary, Pillai, Edward R
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Sprache:eng
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creator Dyckman, Warren D
LaFontant, Gary
Pillai, Edward R
description The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.
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The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.</abstract><oa>free_for_read</oa></addata></record>
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title Clearance hole size adjustment for impedance control in multilayer electronic packaging and printed circuit boards
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