Capacitor with insulating nanostructure

Capacitor with insulating nanostructure

The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. T...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Kellar, Scot A, Kim, Sarah E
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Kellar, Scot A
Kim, Sarah E
description The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07271434</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07271434</sourcerecordid><originalsourceid>FETCH-uspatents_grants_072714343</originalsourceid><addsrcrecordid>eNrjZFB3TixITM4syS9SKM8syVDIzCsuzUksycxLV8hLzMsvLikqTS4pLUrlYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcyNzQxNjEmAglAL_WKYE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Capacitor with insulating nanostructure</title><source>USPTO Issued Patents</source><creator>Kellar, Scot A ; Kim, Sarah E</creator><creatorcontrib>Kellar, Scot A ; Kim, Sarah E ; Intel Corporation</creatorcontrib><description>The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7271434$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7271434$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kellar, Scot A</creatorcontrib><creatorcontrib>Kim, Sarah E</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><title>Capacitor with insulating nanostructure</title><description>The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZFB3TixITM4syS9SKM8syVDIzCsuzUksycxLV8hLzMsvLikqTS4pLUrlYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcyNzQxNjEmAglAL_WKYE</recordid><startdate>20070918</startdate><enddate>20070918</enddate><creator>Kellar, Scot A</creator><creator>Kim, Sarah E</creator><scope>EFH</scope></search><sort><creationdate>20070918</creationdate><title>Capacitor with insulating nanostructure</title><author>Kellar, Scot A ; Kim, Sarah E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_072714343</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Kellar, Scot A</creatorcontrib><creatorcontrib>Kim, Sarah E</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kellar, Scot A</au><au>Kim, Sarah E</au><aucorp>Intel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Capacitor with insulating nanostructure</title><date>2007-09-18</date><risdate>2007</risdate><abstract>The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07271434
source USPTO Issued Patents
title Capacitor with insulating nanostructure
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T23%3A42%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kellar,%20Scot%20A&rft.aucorp=Intel%20Corporation&rft.date=2007-09-18&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07271434%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true