Self-aligned isolation double-gate FET

A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. First...

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Bibliographische Detailangaben

Hauptverfasser:	Chan, Kevin K, Cohen, Guy M, Ieong, Meikei, Roy, Ronnen A, Solomon, Paul M, Yang, Min
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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