Method, system and computer program product for automatically estimating pin locations and interconnect parasitics of a circuit layout

A circuit design technique is provided for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout. The automatically estimating includes automatically generating pin...

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Bibliographische Detailangaben

Hauptverfasser:	Chan, Yiu-Hing, Chu, Jonathan M
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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