Hierarchical memory correction system and method

A hierarchical error correction system and method operable with a computer memory system. In one embodiment, the memory system comprises a plurality of memory modules organized as a number of error correction code (ECC) domains, wherein each ECC domain includes a set of memory modules, each memory m...

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Bibliographische Detailangaben

Hauptverfasser:	Thayer, Larry Jay, Tayler, Michael Kennard
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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